RS422 Interface on Zynq-7000

Overview

This work began as a personal project on the Zynq platform and was later deployed on professional equipment. The goal was to master Zynq-7000 architecture development, which combines FPGA (Programmable Logic) and ARM processor (Processing System), to gain deep understanding of SoC internal operations.

The project develops a multi-channel RS422 frame recording and analysis system with precise timestamping. The primary objective is differential timing measurement between multiple RS422 buses to detect propagation delays and analyze synchronization between equipment.

Technical Objectives

• Implement a configurable multi-channel RS422 receiver in VHDL
• Support both synchronous and asynchronous RS422 reception modes
• Achieve precise data timestamping (1µs resolution) for differential timing analysis between buses
• Record frames for analysis and future replay capability
• Interface FPGA logic (PL) with ARM processor (PS) via AXI-Lite bus
• Develop bare-metal C application for data handling
• Develop Python server application for centralized control and data management

System Architecture

The architecture is built around a Xilinx Zynq-7000, a hybrid SoC combining an ARM processor (PS) with FPGA fabric (PL). Inter-subsystem communication uses the AXI-Lite bus, allowing Linux execution on the ARM while deploying real-time RS422 logic in the FPGA.

A Python server running on a Radxa Rock 3C board controls the entire system via LwIP (Lightweight IP) stack on the Zynq SoC, providing remote control and centralized data management.

┌─────────────────────────────────────────────────┐
│              ZYNQ-7000 SoC                      │
│                                                 │
│  ┌───────────────┐         ┌─────────────────┐  │
│  │  PS (ARM)     │         │   PL (FPGA)     │  │
│  │               │  AXI    │                 │  │
│  │ - Bare-metal  │◄───────►│ - RS422 RX      │  │
│  │ - C App       │  Lite   │ - Clock Gen     │  │
│  │ - LwIP client │  32-bit │ - FIFO Buffers  │  │
│  └──────┬────────┘         └────────┬────────┘  │
│         │                           │           │
└─────────┼───────────────────────────┼───────────┘
          │                           │
     [Ethernet/LwIP]           [RS422 Transceivers]
          │                    [3x ISL83078]
          │
    ┌─────▼─────────┐
    │  Rock 3C      │
    │               │
    │ - Python      │
    │ - TCP Server  │
    │ - Control UI  │
    └───────────────┘

VHDL Development (PL Part)

System Architecture

The FPGA design is organized into several modules:

1. RS422 Serial Block

• Synchronous and asynchronous RS422 reception
• Configurable baud rate from 1 kbps to 16 Mbps
• Acquisition modes: Gap detection, Transparent, Sync word
• FIFO buffer with variable size

2. Internal Timer

• 1µs counter for precise frame timestamping
• 8ns counter for fine temporal resolution
• 1PPS generator for synchronization (Reserved for future use)

3. Serial Handler

• Interface between RS422 serial block and internal timer
• Timestamp capture and association with received frames
• Sync/async multiplexing management

4. AXI Interface

• Configuration management via AXI-Lite
• Data management via AXI-Stream
• Timestamped frame recording in AXI buffers
• Interface with ARM processor for C retrieval

Timestamping and Differential Dating

The internal timer generates two independent counters:

• 1µs Counter: Used for timestamping received frames
• 8ns Counter: High resolution for fine delay measurements

At each frame reception, the system simultaneously captures both timestamps, enabling:

• Absolute timestamping of each frame on each bus
• Calculation of temporal differences between buses (differential dating)
• Analysis of synchronization and data propagation delays in equipment

C Development (PS Part)

AXI DMA Interface

The C application uses AXI DMA to transfer frames from FPGA to DDR memory. The system operates in bare-metal mode with interrupt handling.

At each frame reception, an interrupt triggers:

• Reading timestamped data from DMA buffer
• Retrieving timestamps (1µs + 8ns)

This allows periodic export to Python server via TCP/IP (LwIP)

Electronic Circuit

Custom Arduino Uno Shield

The PYNQ-Z1 board has an Arduino Uno compatible connector, allowing interfacing with standard shields. A prototype shield was created, integrating RS422 transceivers and a removable termination resistor.

Three ISL83078 (full-duplex RS422 transceivers) are integrated on the custom shield. The VHDL implementation is scalable to 4 transceivers.

Tools and Environment

FPGA Development

• Vivado Design Suite 2019.x: VHDL synthesis and implementation
• Vivado HLS: AXI IP generation
• VHDL Testbench: Functional simulation
• ILA (Integrated Logic Analyzer): Real-time debugging

Software Development

• Vitis/SDK 2019.x: Bare-metal development environment
• GCC ARM: Cross-compilation for Zynq
• LwIP: Bare-metal TCP/IP stack
• Python: Control server on Rock 3C and various control and test scripts

Testing and Validation

Tests Performed

Possible Improvements

This project lays the foundation for an RS422 analysis system and can be extended with:

• Transmission (Tx) implementation for frame replay/forging or bus set via Python interface
• Migration to Petalinux (embedded Linux with BusyBox) for more flexible management and advanced network tools
• Web monitoring interface for real-time RS422 bus visualization
• PTP synchronization for inter-system absolute timestamping
• Extension to more than 4 RS422 channels
• Anomaly analysis and detection (corruption, sync loss) with alerts

Skills Developed

Lessons Learned

This project allowed me to understand the Zynq-7000 architecture and FPGA/CPU integration. The main challenge was managing and debugging the PL/PS interface via AXI.

Key takeaways:

• Understanding of AXI bus (Lite and Stream)
• Bare-metal development with interrupt and DMA handling
• Modular VHDL design with testbench for validation
• RS422 hardware interfacing (differential, transceivers)

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